Table 130. Rng Interrupt Requests - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
22.4 RNG interrupts
In the RNG an interrupt can be produced on the following events:
•
Data ready flag
• Seed error, see
•
Clock error, see
Dedicated interrupt enable control bits are available as shown in
Interrupt acronym
RNG
The user can enable or disable the above interrupt sources individually by changing the
mask bits or the general interrupt control bit IE in the RNG_CR register. The status of the
individual interrupt sources can be read from the RNG_SR register.
Note: Interrupts are generated only when RNG is enabled.
22.5 RNG processing time
In recommended configuration A described in
32-bit data is either:
•
206 x N AHB cycles if f
• 128 x N RNG cycles f
With f
threshold
Note: When CLKDIV is different from zero, f
If configuration B is selected the performance figures become:
•
206 AHB cycles if f
•
32 RNG cycles f
with f
threshold
22.6 RNG entropy source validation
22.6.1 Introduction
In order to assess the amount of entropy available from the RNG, STMicroelectronics has
tested the peripheral using the German BSI AIS-31 statistical tests (T0 to T8), and NIST
SP800-90B test suite. The results can be provided on demand or the customer can
reproduce the tests.
Section 22.3.7: Error management
Section 22.3.7: Error management

Table 130. RNG interrupt requests

Interrupt event Event flag
Data ready flag
Seed error flag
Clock error flag
AHB
≥ f
AHB
= 1.6 x f , for instance 77 MHz if f
RNG
< f
AHB threshold
≥ f
AHB threshold
= 6.5 x f .
RNG
True random number generator (RNG)
Enable control bit
DRDY IE
SEIS IE
CEIS IE
Table 131, the time between two sets of four
< f (conditioning stage is limiting), or
threshold
(noise source stage is limiting).
threshold
RNG
must take into account the internal divider ratio.
RNG
or
RM0453 Rev 5
Table 130.
Interrupt clear method
None (automatic)
Write 0 to SEIS or write
CONDRST to 1 then to 0
Write 0 to CEIS
= 48 MHz.Value N is 2.
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