STMicroelectronics STM32WL5 Series Reference Manual page 638

True random number generator (RNG)
Figure 100
1. Writing bits RNGEN = 0 and CONDRST = 1 in the RNG_CR register with the same
RNG configuration and a new CLKDIV if needed.
2. Then writing RNGEN = 1 and CONDRST = 0 in the RNG_CR register.
3. Wait for random number to be ready, after initialization completes.
Note: When the RNG peripheral is reset through RCC (hardware reset), the RNG configuration for
optimal randomness is lost in the RNG registers. Software reset with CONFIGLOCK set
preserves the RNG configuration.
22.3.5 RNG operation
Normal operations
To run the RNG using interrupts, the following steps are recommended:
1. Consult
configuration is required for the application.
–
–
2. An interrupt is now generated when a random number is ready or when an error
occurs. Therefore, at each interrupt, check that:
–
–
–
To run the RNG in polling mode following steps are recommended:
1. Consult
configuration is required for the application.
–
–
2. Read the RNG_SR register and check that:
–
–
3. If above conditions are true read the content of the RNG_DR register up to four
consecutive times. If valid data is available in the conditioning output buffer four
638/1450
also highlights a possible software reset sequence, implemented by:
Section 22.6: RNG entropy source validation
If it is the case, write in the RNG_CR register the bit CONDRST = 1 together with
the correct RNG configuration. Then perform a second write to the RNG_CR
register with the bit CONDRST = 0, the interrupt enable bit IE = 1 and the RNG
enable bit RNGEN = 1.
If it is not the case perform a write to the RNG_CR register with the interrupt
enable bit IE = 1 and the RNG enable bit RNGEN = 1.
No error occurred. The SEIS and CEIS bits must be set to 0 in the RNG_SR
register.
A random number is ready. The DRDY bit must be set to 1 in the RNG_SR
register.
If the above two conditions are true the content of the RNG_DR register can be
read up to four consecutive times. If valid data is available in the conditioning
output buffer, four additional words can be read by the application (in this case the
DRDY bit is still high). If one or both of the above conditions are false, the
RNG_DR register must not be read. If an error occurred, the error recovery
sequence described in
Section 22.6: RNG entropy source validation
If it is the case write in the RNG_CR register the bit CONDRST = 1 together with
the correction RNG configuration. Then perform a second write to the RNG_CR
register with the bit CONDRST = 0 and the RNG enable bit RNGEN = 1.
If it is not the case only enable the RNG by setting the RNGEN bit to 1 in the
RNG_CR register.
No error occurred (the SEIS and CEIS bits must be set to 0)
A random number is ready (the DRDY bit must be set to 1)
Section 22.3.7 must be used.
RM0453 Rev 5
and verify if a specific RNG
and verify if a specific RNG
RM0453