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Global security controller (GTZC)
3.5.2
GTZC TZSC security configuration register
(GTZC_TZSC_SECCFGR1)
Address offset: 0x010
Reset value: 0x0000 0000
Secure write access only.
A bit of this register can be written only by a secure privileged transaction, when the
corresponding bit in GTZC_TZSC_PRIVCFGR1 is set to privileged. If unprivileged, the
register bit can be written by secure privileged and secure unprivileged transactions.
Read access is authorized for any type of transaction, secure/non-secure,
privileged/unprivileged.
An illegal access event on a privileged access is only generated when all peripheral register
bits in GTZC_TZSC_PRIVCFGR1 are configured as privileged.
When TZSC configuration is locked in GTZC_TZSC_CR.LCK, this register can no longer be
modified.
Note:
When the system is non-secure (ESE = 0) this register cannot be written and is read zero.
Peripherals cannot be secured.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
PKA
Res.
Res.
Res.
SEC
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PKASEC: Secure access mode enabled for PKA
Bits 12:4 Reserved, must be kept at reset value.
Bit 3 RNGSEC: Secure access mode enabled for RNG
Bit 2 AESSEC: Secure access mode enabled for AES
Bits 1:0 Reserved, must be kept at reset value.
86/1450
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
0: Non-secure
1: Secure
0: Non-secure
1: Secure
0: Non-secure
1: Secure
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
RNG
AES
Res.
Res.
SEC
SEC
rw
rw
RM0453
17
16
Res.
Res.
1
0
Res.
Res.
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