Security Illegal Access Controller (Tzic); Power-On/Reset State; Figure 6. Memory Protection Control Water Mark - STMicroelectronics STM32WL5 Series Reference Manual

Global security controller (GTZC)
address with a length defined through
GTZC_TZSC_MPCWM1_UPWWMR.LGTH[11:0]. Only the area which is also defined
as unprivileged in GTZC_TZSC_MPCWM1_UPWMR.LGTH[11:0] is unprivileged
writable.
Note: Where n represents the target memory (1 = Flash memory, 2 = SRAM1 and 3 = SRAM2).
3.4.5

Security illegal access controller (TZIC)

This block concentrates all illegal access source events. It is used only when the system is
security enabled (ESE = 1). When the system is non-secure (ESE = 0), the generation of an
illegal access interrupt is blocked in hardware.
TZIC allows the trace of which event has trigged the illegal interrupt tzic_ila_it. Register
masks are available in TZIC_IER to filter unwanted events. Enabled illegal events generate
an interrupt to the secure CPU2 NVIC (TZIC_ILA).
For each illegal event source, a status flag and a clear bit exist (respectively within
TZIC_MISR and TZIC_ICR registers). The reset value of the enable register TZIC_IER is
such that all illegal events are enabled.
3.4.6

Power-on/reset state

The power-on and reset state of TZSC clear all bits of SECCFGR1 and PRIVCFGR1
registers to 0, which respectively means non-secure and unprivileged.
Concerning the internal memories, the reset values of the TZSC MPCWMn_UPWMR and
MPCWMn_UPWWMR registers are set to 0x0FFF 0000, making the complete internal
memories unprivileged.
CPU1 non-secure privileged boot code can program the non-secure privileged attributes,
making components non-secure privileged as needed.
CPU2 secure privileged boot code can program the secure privileged attributes, making
components secure privileged as needed.
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Figure 6. Memory protection control water mark

Memory base address
RM0453 Rev 5
Privileged
Privileged and
unprivileged
read, execute
Unprivileged
read, execute
and
writable
RM0453
MSv61500V1