STMicroelectronics STM32WL5 Series Reference Manual page 382

Hardware semaphore (HSEM)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ISF[15:0]: Interrupt semaphore x status bit before enable (mask) (x = 0 to 15)
8.4.6 HSEM interrupt status register (HSEM_CnMISR)
Address offset: 0x10C + 0x010 * (n - 1), (n = 1 to 2)
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 MISF[15:0]: Masked interrupt(n) semaphore x status bit after enable (mask) (x = 0 to 15)
8.4.7 HSEM clear register (HSEM_CR)
Address offset: 0x140
Reset value: 0x0000 0000
Only write accesses with authorized AHB bus master IDs are granted. Write accesses with
unauthorized AHB bus master IDs are discarded.
31 30 29
w w w
15 14 13
Res. Res. Res. Res.
Bits 31:16 KEY[15:0]: Semaphore clear key
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This bit is set by hardware, and reset only by software. This bit is cleared by software writing
the corresponding HSEM_CnICR bit.
0: Interrupt semaphore x status, no interrupt pending
1: Interrupt semaphore x status, interrupt pending
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
This bit is set by hardware and read only by software. This bit is cleared by software writing
the corresponding HSEM_CnICR bit. This bit is read as 0 when semaphore x status is
masked in HSEM_CnIER bit x.
0: interrupt(n) semaphore x status after masking not pending
1: interrupt(n) semaphore x status after masking pending
28 27 26 25
w w w w
12 11 10 9
COREID[3:0]
w w w
This field can be written by software and is always read 0.
If this key value does not match HSEM_KEYR.KEY, semaphores are not affected.
If this key value matches HSEM_KEYR.KEY, all semaphores matching the COREID are
cleared to the free state.
24 23 22
Res. Res. Res.
8 7 6
MISF[15:0]
r r r
24 23 22
KEY[15:0]
w w w
8 7 6
Res. Res.
w
RM0453 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
r r r r
21 20 19 18
w w w w
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
Res. Res.
1 0
r r
17 16
w w
1 0
Res. Res.