Figure 50. Dmamux Block Diagram - STMicroelectronics STM32WL5 Series Reference Manual

DMA request multiplexer (DMAMUX)
14.4 DMAMUX functional description
14.4.1 DMAMUX block diagram
Figure 50
DMAMUX
To secure
interrupt
controller:
dmamux_ilac
DMA requests
from peripherals:
dmamux_req_inx
Control registers
DMAMUX features two main sub-blocks: the request line multiplexer and the request line
generator.
The implementation assigns:
•
DMAMUX request multiplexer sub-block inputs (dmamux_reqx) from peripherals
(dmamux_req_inx) and from channels of the DMAMUX request generator sub-block
(dmamux_req_genx)
• DMAMUX request outputs to channels of DMA controllers (dmamux_req_outx)
•
Internal or external signals to DMA request trigger inputs (dmamux_trgx)
• Internal or external signals to synchronization inputs (dmamux_syncx)
484/1450
shows the DMAMUX block diagram.

Figure 50. DMAMUX block diagram

32-bit AHB bus
AHB slave
interface
p
1
0
Request
generator
n
Channel n
DMAMUX_RGCnCR
1
Channel 1
DMAMUX_RGC1CR
0
Channel 0
DMAMUX_RGC0CR
interface
t 1 0
Trigger inputs:
Interrupts:
dmamux_trgx
dmamux_sec_ovr_it,
dmamux_nonsec_ovr_it
dmamux_hclk
Request multiplexer
Channel m
DMAMUX_CmCR
Channel 1
Channel 0
DMAMUX_C0CR
Channel
select
n+p+2
n+3
Sync
n+2
n+1
s
2
1
Interrupt
s
Synchronization inputs:
dmamux_syncx
RM0453 Rev 5
m
1
0
Ctrl
m
DMA requests
1
to DMA controllers:
0
dmamux_req_outx
m
DMA channels events:
1
dmamux_evtx
0
1 0
1 0
RM0453
Secure and
privileged state of
the DMA channels:
dma_secmx
dma_privx
MS51703V2