STMicroelectronics STM32WL5 Series Reference Manual page 133

RM0453
Bit 14 RDERR: PCROP read error
Bit 13 OPTNV: User option OPTVAL indication
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 FASTERR: Fast programming error
Bit 8 MISSERR: Fast programming data miss error
Bit 7 PGSERR: Programming sequence error
Bit 6 SIZERR: Size error
Bit 5 PGAERR: Programming alignment error
Bit 4 WRPERR: Write protection error
Bit 3 PROGERR: Programming error
Set by hardware when an address to be read through the D-bus belongs to a read protected
area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in
FLASH_CR.
This bit is cleared by writing 1.
This bit is set and reset by hardware.
0: The OBL user option OPTVAL indicates "valid" (user option program sequence has not
terminated completely).
1: The OBL user option OPTVAL indicates "not valid" (OPTVAL check word has been
erroneously read).
Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted
due to an error (alignment, size, write protection or data miss). The corresponding status bit
(PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time.
This bit is cleared by writing 1.
In Fast programming mode, 32 double-words (256 bytes) must be sent to the flash memory
successively and the new data must be sent to the logic control before the current data is
fully programmed.
This bit is set by hardware when the new data is not present in time and cleared by writing 1.
This bit is set by hardware when a write access to the flash memory is performed by the
code, while PG or FSTPG have not been set previously. This bit is also set by hardware
when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a
previous programming error.
This bit is cleared by writing 1.
This bit is set by hardware when the size of the access is a byte or half-word during a
program or a fast program sequence. Only double-word programming is allowed
(consequently: word access).
This bit is cleared by writing 1.
This bit is set by hardware when the data to program cannot be contained in the same
double-word (64 bits) flash memory in case of standard programming, or if there is a change
of page during fast programming.
This bit is cleared by writing 1.
This bit is set by hardware when an address to be erased/programmed belongs to a write-
protected part (by WRP, PCROP or RDP level 1) of the flash memory.
This bit is cleared by writing 1.
This bit is set by hardware when a double-word address to be programmed contains a value
different from 0xFFFF FFFF FFFF FFFF before programming, except if the data to write is
0x0000 0000 0000 0000.
This bit is cleared by writing 1.
RM0453 Rev 5
Embedded flash memory (FLASH)
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