Figure 176. Clearing Timx Ocxref - STMicroelectronics STM32WL5 Series Reference Manual

Advanced-control timer (TIM1)
25.3.18 Clearing the OCxREF signal on an external event
The OCxREF signal of a given channel can be cleared when a high level is applied on the
ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1).
OCxREF remains low until the next transition to the active state, on the following PWM
cycle. This function can only be used in Output compare and PWM modes. It does not work
in Forced mode. ocref_clr_int input can be selected between the OCREF_CLR input and
ETRF (ETR after the filter) by configuring the OCCS bit in the TIMx_SMCR register.
When ETRF is chosen, ETR must be configured as follows:
1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR
register set to '00'.
2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
'0'.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
Figure 176
for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.
Counter (CNT)
(OCxCE = '0')
(OCxCE = '1')
Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at
the next counter overflow.
766/1450
shows the behavior of the OCxREF signal when the ETRF Input becomes High,

Figure 176. Clearing TIMx OCxREF

(CCRx)
ETRF
OCxREF
OCxREF
ocref_clr_int ocref_clr_int
becomes high
RM0453 Rev 5
still high
RM0453
MS33105V2