Gtzc Tzic Interrupt Status Clear Register 1 (Gtzc_Tzic_Icr1) - STMicroelectronics STM32WL5 Series Reference Manual

Global security controller (GTZC)
3.6.3

GTZC TZIC interrupt status clear register 1 (GTZC_TZIC_ICR1)

Address offset: 0x020
Reset value: 0x0000 0000
This register can only be access by a secure privileged access for read and write. A non
secure or unprivileged access is ignored and return zero data and an illegal access event is
generated.
Note: When the system is non-secure (ESE = 0), this register cannot be written and reads zero.
31 30 29
Res. Res. Res. Res.
15 14 13
SRAM2
Res. Res. PKACF
rc_w1 rc_w1
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PKACF: Illegal access event interrupt status flag clear bit for PKA
Bit 12 SRAM2CF: Illegal access event interrupt status flag clear bit for SRAM2
Bit 11 SRAM1CF: Illegal access event interrupt status flag clear bit for SRAM1
Bit 10 FLASHCF: Illegal access event interrupt status flag clear bit for flash memory
Bit 9 DMAMUX1CF: Illegal access event interrupt status flag clear bit for DMAMUX1
Bit 8 DMA2CF: Illegal access event interrupt status flag clear bit for DMA2
Bit 7 DMA1CF: Illegal access event interrupt status flag clear bit for DMA1
Bit 6 FLASHIFCF: Illegal access event interrupt status flag clear bit for flash interface
Bit 5 PWRCF: Illegal access event interrupt status flag clear bit for PWR
96/1450
28 27 26 25
Res. Res. Res.
12 11 10 9
SRAM1 FLASH DMAM
CF CF CF UX1CF
rc_w1 rc_w1 rc_w1
0: No action
1: Clear status flag
0: No action
1: Clear status flag
0: No action
1: Clear status flag
0: No action
1: Clear status flag
0: No action
1: Clear status flag
0: No action
1: Clear status flag
0: No action
1: Clear status flag
0: No action
1: Clear status flag
0: No action
1: Clear status flag
24 23 22
Res. Res. Res.
8 7 6
DMA2 DMA1 FLASHI PWR
CF CF FCF
rc_w1 rc_w1 rc_w1 rc_w1
RM0453 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
SUBG
RNG
HZSPI AESCF
CF CF
CF
rc_w1 rc_w1 rc_w1
RM0453
17 16
Res. Res.
1 0
TZSC TZIC
CF CF
rc_w1 rc_w1