STMicroelectronics STM32WL5 Series Reference Manual page 242

Power control (PWR)
radio may remain active independently from the CPUs.
Some peripherals with the wake-up capability can enable HSI16 RC during the Stop
mode to detect their wake-up condition.
Stop 1 offers the largest number of active peripherals and wake-up sources, a smaller
wake-up time but a higher consumption compared with Stop 2.
In Stop 0 mode, the main regulator remains on, resulting in the fastest wake-up time
but with much higher consumption. The active peripherals and wake-up sources are
the same as in Stop 1 mode that uses the low-power regulator.
The system clock, when exiting Stop 0 or Stop 1 mode, can be either MSI up to 48 MHz
or HSI16, depending on the software configuration.
• Stop 2
and some peripherals preserve their contents (see
on system operating
All clocks in the V
LSI and LSE can be kept running.
RTC can remain active (Stop 2 mode with RTC, Stop 2 mode without RTC). The sub-
GHz radio may also remain active independent from the CPUs.
Some peripherals with the wake-up capability can enable HSI16 RC during the Stop 2
mode to detect their wake-up condition (see
system operating
The system clock when exiting from Stop 2 mode, can be either MSI up to 48 MHz or
HSI16, depending on the software configuration.
•
Standby
SRAM2 content as detailed below:
–
–
All clocks in the V
LSI and LSE can be kept running.
Th RTC can remain active (Standby mode with RTC, Standby mode without RTC). The
sub-GHz radio and the PVD may also remain active when enabled independent from
the CPUs. In Standby mode, the PVD selects its lowest level.
The system clock, when exiting Standby modes, is MSI at 4 MHz.
•
Shutdown
stopped. PLL, MSI, HSI16, LSI and HSE32 are disabled. LSE can be kept running. The
system clock when exiting the Shutdown mode, is MSI at 4 MHz. In this mode, the
supply voltage monitoring is disabled and the product behavior is not guaranteed in
case of a power voltage drop.
Note: Stop, Standby and Shutdown modes are only entered when both CPUs are in CStop mode.
When the device boot in RSS/SFI mode, the low-power modes Stop, Standby and
Shutdown, cannot be entered.
In addition, the power consumption in Run mode can be reduced by slowing down the
system clocks, and/or by gating the clocks to the APB and AHB peripherals when they are
unused.
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mode: part of the V
mode).
domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.
CORE
mode).
mode: V domain is powered off. However, it is possible to preserve the
CORE
Standby mode with SRAM2 retention when the RRS bit is set in the
register 3 (PWR_CR3). In this case, SRAM2 is supplied by the low-power
regulator.
Standby mode when the RRS bit is cleared in the
(PWR_CR3). In this case the main regulator and the low-power regulator are
powered off.
domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.
CORE
mode: V domain is powered off. All clocks in the V
CORE
domain is powered off. Only SRAM1, SRAM2, CPUs
CORE
Table 45: Functionalities depending on
RM0453 Rev 5
Table 45: Functionalities depending
PWR control register 3
domain are
CORE
RM0453
PWR control