STMicroelectronics STM32WL5 Series Reference Manual page 576

Analog-to-digital converter (ADC)
18.12.4 ADC configuration register 1 (ADC_CFGR1)
Address offset: 0x0C
Reset value: 0x0000 0000
The software is allowed to program ADC_CFGR1 only when ADEN is cleared in ADC_CR.
31 30 29
Res. AWD1CH[4:0]
rw rw
15 14 13
AUTOF OVRM
WAIT CONT
F
rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:26 AWD1CH[4:0]: Analog watchdog channel selection
These bits are set and cleared by software. They select the input channel to be guarded by
the analog watchdog.
00000: ADC analog input Channel 0 monitored by AWD
00001: ADC analog input Channel 1 monitored by AWD
.....
10001: ADC analog input Channel 17 monitored by AWD
Others: Reserved
Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR
Bits 25:24 Reserved, must be kept at reset value.
Bit 23 AWD1EN: Analog watchdog enable
This bit is set and cleared by software.
0: Analog watchdog 1 disabled
1: Analog watchdog 1 enabled
Note:
Bit 22 AWD1SGL: Enable the watchdog on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel
identified by the AWDCH[4:0] bits or on all the channels
0: Analog watchdog 1 enabled on all channels
1: Analog watchdog 1 enabled on a single channel
Note:
Bit 21 CHSELRMOD: Mode selection of the ADC_CHSELR register
This bit is set and cleared by software to control the ADC_CHSELR feature:
0: Each bit of the ADC_CHSELR register enables an input
1: ADC_CHSELR register is able to sequence up to 8 channels
Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register
Bits 20:17 Reserved, must be kept at reset value.
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28 27 26 25
Res.
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12 11 10 9
EXTEN[1:0] Res.
OD
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register.
or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
24 23 22
AWD1E AWD1S CHSEL
Res.
N GL RMOD
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8 7 6
EXTSEL[2:0] ALIGN
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RM0453 Rev 5
21 20 19 18
Res. Res. Res.
rw
5 4 3 2
SCAND
RES[1:0]
IR
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RM0453
17 16
DISCE
Res.
N
rw
1 0
DMAC DMAE
FG N
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