STMicroelectronics STM32WL5 Series Reference Manual page 443

RM0453
11.2.14 SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2)
Address offset: 0x10C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
DMAM DMA2C DMA2C DMA2C
UX1IM H7IM H6IM H5IM
rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 PVDIM: PVD interrupt mask to CPU2
0: PVD interrupt forwarded to CPU2
1. PVD interrupt to CPU2 masked
Bit 19 Reserved, must be kept at reset value.
Bit 18 PVM3IM: PVM3 interrupt mask to CPU2
0: PVM3 interrupt forwarded to CPU2
1. PVM3 interrupt to CPU2 masked.
Bits 17:16 Reserved, must be kept at reset value.
Bit 15 DMAMUX1IM: DMAMUX1 interrupt mask to CPU2
0: DMAMUX1 interrupt forwarded to CPU2
1. DMAMUX1 interrupt to CPU2 masked
Bits 14:8 DMA2CHxIM: DMA2CHx interrupt mask to CPU2 (x = 7 to 1)
0: DMA2CHx interrupt forwarded to CPU2
1. DMA2CHx interrupt to CPU2 masked
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 DMA1CHxIM: DMA1CHx interrupt mask to CPU2 (x = 7 to 1)
0: DMA1CHx interrupt forwarded to CPU2
1. DMA1CHx interrupt to CPU2 masked
11.2.15 SYSCFG radio debug control register (SYSCFG_RFDCR)
Address offset: 0x208
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
28 27 26 25
Res. Res. Res.
12 11 10 9
DMA2C DMA2C DMA2C
H4IM H3IM H2IM
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
System configuration controller (SYSCFG)
24 23 22
Res. Res. Res.
8 7 6
DMA2C DMA1C DMA1C
Res.
H1IM H7IM H6IM
rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 5
21 20 19 18
PVM3I
Res. PVDIM Res.
M
rw rw
5 4 3 2
DMA1C DMA1C DMA1C
H5IM H4IM H3IM
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
17 16
Res. Res.
1 0
DMA1C DMA1C
H2IM H1IM
rw rw
17 16
Res. Res.
1 0
RFTBS
Res.
EL
rw
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