STMicroelectronics STM32WL5 Series Reference Manual page 386

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Inter-processor communication controller (IPCC)
9
Inter-processor communication controller (IPCC)
9.1
IPCC introduction
The inter-processor communication controller (IPCC) is used for communicating data
between two processors.
The IPCC block provides a nonblocking signaling mechanism to post and retrieve
communication data in an atomic way. It provides the signaling for twelve channels:
six channels in the direction from processor 1 to processor 2
six channels in the opposite direction
It is then possible to have two different communication types in each direction.
The IPCC communication data must be located in a common memory, which is not part of
the IPCC block.
9.2
IPCC main features
Status signaling for the twelve channels
Two interrupt lines per processor
Interrupt masking per channel
Two channel operation modes
9.3
IPCC functional description
The IPCC communication data is located in a common memory, which is not part of the
IPCC block. The address location of the communication data must be known or located in a
known common area that, as already stated, is not part of the IPCC block.
For each communication, the IPCC block provides a channel status flag CHnF.
When 0, the channel status flag CHnF indicates that the associated IPCC channel is
free (the receiving processor has retrieved communication data), and can be accessed
by the sending processor.
When 1, the channel status flag CHnF indicates that the associated IPCC channel is
occupied (the sending processor has posted communication data) and can be
accessed by the receiving processor.
386/1450
Channel occupied/free flag, also used as lock
One for RX channel occupied (communication data posted by sending processor)
One for TX channel free (communication data retrieved by receiving processor)
Channel occupied mask
Channel free mask
Simplex (each channel has its own communication data memory location)
Half duplex (a single channel associated to a bidirectional communication data
information memory location)
RM0453 Rev 5
RM0453

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