Figure 194. Counter Timing Diagram, Internal Clock Divided By N; Figure 195. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded) - STMicroelectronics STM32WL5 Series Reference Manual

General-purpose timer (TIM2) RM0453

Figure 194. Counter timing diagram, internal clock divided by N

CK_PSC
Timerclock = CK_CNT
1F
Counter register 00
20
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31081V2
Figure 195. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)
CK_PSC
CEN
Timerclock = CK_CNT
31 32 33 34 35 36 00 01 02 03 04 05 06 07
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
Auto-reload preload
FF 36
register
Write a new value in TIMx_ARR
MS31082V2
828/1450 RM0453 Rev 5