STMicroelectronics STM32WL5 Series Reference Manual page 793

RM0453
Bit 2 CC2G: Capture/Compare 2 generation
Refer to CC1G description
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. The prescaler internal
25.4.7 TIM1 capture/compare mode register 1(TIM1_CCMR1)
Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section). The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function for input capture and for
output compare modes. It is possible to combine both modes independently (e.g. channel 1
in input capture mode and channel 2 in output compare mode).
Input capture mode:
31 30 29
Res. Res. Res. Res.
15 14 13
IC2F[3:0]
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:12 IC2F[3:0]: Input capture 2 filter
Refer to IC1F[3:0] description.
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Refer to IC1PSC[1:0] description.
counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the
center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).
28 27 26 25
Res. Res. Res.
12 11 10 9
IC2PSC[1:0] CC2S[1:0]
rw rw rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
IC1F[3:0]
rw rw rw
RM0453 Rev 5
Advanced-control timer (TIM1)
21 20 19 18
Res. Res. Res.
5 4 3 2
IC1PSC[1:0]
rw rw rw rw
17 16
Res. Res.
1 0
CC1S[1:0]
rw rw
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