STMicroelectronics STM32WL5 Series Reference Manual page 215

RM0453
5.10.26 Sub-GHz radio generic node address register
(SUBGHZ_GNODEADR)
Address offset: 0x6CD
Reset value: 0x00
7 6
rw rw
Bits 7:0 NODEADD[7:0]: Node address used in FSK mode register
5.10.27 Sub-GHz radio generic broadcast address register
(SUBGHZ_GBCASTADDR)
Address offset: 0x6CE
Reset value: 0x00
7 6
rw rw
Bits 7:0 BCASTADD[7:0]: Broadcast address used in FSK mode register
5.10.28 Sub-GHz radio generic AFC register (SUBGHZ_GAFCR)
Address offset: 0x6D1
Reset value: 0x18
7 6
rw rw
Bits 7:0 AFC[7:0]: Automatic frequency control register
5.10.29 Sub-GHz radio LoRa payload length register
(SUBGHZ_LPLDLENR)
Address offset: 0x702
Reset value: 0x00
7 6
rw rw
Bits 7:0 PLDLEN[7:0]: Payload length in number of bytes, in case of LoRa fixed header
5 4
NODEADD[7:0]
rw rw
5 4
BCASTADD[7:0]
rw rw
5 4
AFC[7:0]
rw rw
5 4
PLDLEN[7:0]
rw rw
RM0453 Rev 5
Sub-GHz radio (SUBGHZ)
3 2
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3 2
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3 2
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3 2
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1 0
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1 0
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1 0
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1 0
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