Figure 126. Dma Transfer Of A 128-Bit Data Block During Output Phase - STMicroelectronics STM32WL5 Series Reference Manual

RM0453

Figure 126. DMA transfer of a 128-bit data block during output phase

Word3
DOUT[127:96]
D127
MSB
DMA
DMA req N
single read
1
(No swapping)
1
O127
MSB
1 4
Order of read from AES_DOUTR
DMA operation in different operating modes
DMA operations are usable when Mode 1 (encryption) or Mode 3 (decryption) are selected
via the MODE[1:0] bitfield of the register AES_CR. As in Mode 2 (key derivation) the
AES_KEYRx registers must be written by software, enabling the DMA transfer through the
DMAINEN and DMAOUTEN bits of the AES_CR register have no effect in that mode.
DMA single requests are generated by AES until it is disabled. So, after the data output
phase at the end of processing of a 128-bit data block, AES switches automatically to a new
data input phase for the next data block, if any.
When the data transferring between AES and memory is managed by DMA, the CCF flag
has no use because the reading of the AES_DOUTR register is managed by DMA
automatically at the end of the computation phase. The CCF flag must only be cleared when
transiting back to data transferring managed by software. See
procedure to perform a cipher
23.4.17 AES error management
AES configuration can be changed at any moment by clearing the EN bit of the AES_CR
register.
Read error flag (RDERR)
Unexpected read attempt of the AES_DOUTR register sets the RDERR flag of the AES_SR
register, and returns zero.
RDERR is triggered during the computation phase or during the input phase.
Note: AES is not disabled upon a RDERR error detection and continues processing.
An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details,
refer to Section 23.5: AES
The RDERR flag is cleared by setting the ERRIE bit of the AES_CR register.
Write error flag (WDERR)
Unexpected write attempt of the AES_DINR register sets the WRERR flag of the AES_SR
register, and has no effect on the AES_DINR register. The WRERR is triggered during the
computation phase or during the output phase.
Chronological order
Increasing address
Memory accessed through DMA
Word2
DOUT[95:64]
D96 D95
DMA
DMA req N+1
single read
2
2
AES core output buffer
O96 O95
operation, subsection
interrupts.
Word1
DOUT[63:32]
D64 D63
DMA
DMA req N+2
single read
3
AES_DOUTR
3
O64 O63
Data
RM0453 Rev 5
AES hardware accelerator (AES)
Word0
DOUT[31:0]
D32 D31
DMA
DMA req N+3
single read
4
4
O32 O31
Section 23.4.4: AES
append, for details.
D0
LSB
O0
LSB
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