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System window watchdog (WWDG)
Bit 9 EWI: Early wake-up interrupt enable
Bits 8:7 Reserved, must be kept at reset value.
Bits 6:0 W[6:0]: 7-bit window value
31.5.3
WWDG status register (WWDG_SR)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 EWIF: Early wake-up interrupt flag
31.5.4
WWDG register map
The following table gives the WWDG register map and reset values.
Register
Offset
name
WWDG_CR
0x000
Reset value
WWDG_CFR
0x004
Reset value
WWDG_SR
0x008
Reset value
Refer to
988/1450
Set by software and cleared by hardware after a reset. When set, an interrupt occurs
whenever the counter reaches the value 0x40.
These bits contain the window value to be compared with the down-counter.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared
by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not
enabled.
Table 206. WWDG register map and reset values
Section 2.6 on page 71
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
for the register boundary addresses.
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
0
1
WDGTB
[2:0]
0
0
0
0
1
RM0453
17
16
Res.
Res.
1
0
Res.
EWIF
rc_w0
T[6:0]
1
1
1
1
1
1
W[6:0]
1
1
1
1
1
1
0
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