STMicroelectronics STM32WL5 Series Reference Manual page 972

Low-power timer (LPTIM)
Table 203. LPTIM register map and reset values (continued)
Offset Register name
LPTIM_CR
0x010
Reset value
LPTIM_CMP
0x014
Reset value
LPTIM_ARR
0x018
Reset value
LPTIM_CNT
0x01C
Reset value
LPTIM1_OR
0x020
Reset value
LPTIM2_OR
0x020
Reset value
LPTIM3_OR
0x020
Reset value
LPTIM_RCR
0x028
Reset value
1. If LPTIM does not support encoder mode feature, this bit is reserved. Refer to
Refer to
972/1450
Section 2.6 on page 71
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Section 28.3: LPTIM
for the register boundary addresses.
RM0453 Rev 5
RM0453
0 0 0 0 0
CMP
[15:0]
ARR[15:0]
CNT[15:0]
0 0
0 0
0 0
REP[7:0]
0 0 0 0 0 0 0 0
implementation.