STMicroelectronics STM32WL5 Series Reference Manual page 335

RM0453
7.4.23 RCC AHB2 peripheral clock enable in Sleep mode register
(RCC_AHB2SMENR)
Address offset: 0x06C
Reset value: 0x0000 0087
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 GPIOHSMEN: IO port H clock enable during CPU1 CSleep mode.
This bit is set and cleared by software.
0: IO port H clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: IO port H clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode.
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 GPIOCSMEN: IO port C clock enable during CPU1 CSleep mode.
This bit is set and cleared by software.
0: IO port C clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: IO port C clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
Bit 1 GPIOBSMEN: IO port B clock enable during CPU1 CSleep mode.
This bit is set and cleared by software.
0: IO port B clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: IO port B clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
Bit 0 GPIOASMEN: IO port A clock enable during CPU1 CSleep mode.
This bit is set and cleared by software.
0: IO port A clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: IO port A clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
GPIOH
Res. Res.
SMEN
rw
RM0453 Rev 5
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
GPIOC
Res. Res. Res.
SMEN
rw
17 16
Res. Res.
1 0
GPIOB GPIOA
SMEN SMEN
rw rw
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