Table 139. Aes Interrupt Requests; Table 140. Processing Latency For Ecb, Cbc And Ctr - STMicroelectronics STM32WL5 Series Reference Manual

AES hardware accelerator (AES)
Note: AES is not disabled after a WRERR error detection and continues processing.
An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details,
refer to Section 23.5: AES
The WRERR flag is cleared by setting the ERRC bit of the AES_CR register.
23.5 AES interrupts
Individual maskable interrupt sources generated by the AES peripheral signal the following
events:
• computation completed
•
read error
• write error
These sources are combined into a common interrupt signal from the AES peripheral that
connects to the Arm
enabled/disabled, by setting/clearing the corresponding enable bit of the AES_CR register,
and cleared by setting the corresponding bit of the AES_CR register.
The status of each can be read from the AES_SR register.
Table 139
Interrupt
AES interrupt event
acronym
AES computation completed flag
1. Bit of the AES_CR register.
23.6 AES processing latency
The tables below summarize the latency to process a 128-bit block for each mode of
operation.
Key size
Mode 1: Encryption
128-bit
Mode 2: Key derivation
Mode 3: Decryption
Mode 1: Encryption
256-bit
Mode 2: Key derivation
Mode 3: Decryption
682/1450
interrupts.
® ®
Cortex interrupt controller. Each can individually be
gives a summary of the interrupt sources, their event flags and enable bits.

Table 139. AES interrupt requests

read error flag
write error flag

Table 140. Processing latency for ECB, CBC and CTR

Mode of operation
Event flag
CCF
RDERR
WRERR
RM0453 Rev 5
Interrupt clear
Enable bit
method
CCFIE set CCFC
ERRIE set ERRC
Algorithm
ECB, CBC, CTR
-
ECB, CBC, CTR
ECB, CBC, CTR
-
ECB, CBC, CTR
RM0453
(1)
(1)
Clock
cycles
51
59
51
75
82
75