Table 238. I2C Register Map And Reset Values - STMicroelectronics STM32WL5 Series Reference Manual

Inter-integrated circuit (I2C) interface
34.7.11 I2C transmit data register (I2C_TXDR)
Address offset: 0x28
Reset value: 0x0000 0000
Access: No wait states
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 TXDATA[7:0]: 8-bit transmit data
Note: These bits can be written only when TXE = 1.
34.7.12 I2C register map
The table below provides the I2C register map and reset values.
Register
Offset
name
I2C_CR1
0x0
Reset value
I2C_CR2
0x4
Reset value
I2C_OAR1
0x8
Reset value
I2C_OAR2
0xC
Reset value
I2C_
TIMINGR
0x10
Reset value
1112/1450
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Data byte to be transmitted to the I

Table 238. I2C register map and reset values

0 0 0
PRESC[3:0]
0 0 0 0
24 23 22
Res. Res. Res.
8 7 6
Res.
rw rw
2
C bus
0 0 0 0 0 0 0 0 0
NBYTES[7:0]
0 0 0 0 0 0 0 0 0
0
0
SCLDEL SDADEL
[3:0] [3:0]
0 0 0 0 0 0 0 0 0
RM0453 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3
TXDATA[7:0]
rw rw rw rw
DNF[3:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0
OA2MS
K [2:0]
0 0 0 0 0
SCLH[7:0]
0 0 0 0 0 0 0 0 0
RM0453
17 16
Res. Res.
2 1 0
rw rw
0 0 0 0 0 0
SADD[9:0]
0 0 0 0 0 0
OA1[9:0]
0 0 0 0 0 0
OA2[7:1]
0 0 0 0 0
SCLL[7:0]
0 0 0 0 0 0