STMicroelectronics STM32WL5 Series Reference Manual page 356

Reset and clock control (RCC)
Bit 5 LPTIM2EN: CPU2 low-power timer 2 clocks enable
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 LPUART1EN: CPU2 low-power UART 1 clocks enable
7.4.38 RCC CPU2 APB2 peripheral clock enable register
(RCC_C2APB2ENR)
Address offset: 0x160
Reset value: 0x0000 0000
Access: word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access from
CPU2 is not supported.
31 30 29
Res. Res. Res. Res.
15 14 13
USART1 SPI1
Res. Res.
EN
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: CPU2 timer 17 clock enable
This bit is set and cleared by software.
0: TIM17 clock disabled for CPU2
1: TIM17 clock enabled for CPU2
Bit 17 TIM16EN: CPU2 timer 16 clock enable
This bit is set and cleared by software.
0: TIM16 clock disabled for CPU2
1: TIM16 clock enabled for CPU2
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 USART1EN: CPU2 USART1clocks enable
This bit is set and cleared by software.
0: USART1 bus and kernel clocks disabled for CPU2
1: USART1 bus and kernel clocks enabled for CPU2
Bit 13 Reserved, must be kept at reset value.
356/1450
This bit is set and cleared by software.
0: LPTIM2 bus and kernel clocks disabled for CPU2
1: LPTIM2 bus and kernel clocks enabled for CPU2
This bit is set and cleared by software.
0: LPUART1 bus and kernel clocks disabled for CPU2
1: LPUART1 bus and kernel clocks enabled for CPU2
28 27 26 25
Res. Res. Res.
12 11 10 9
TIM1 ADC
Res.
EN EN EN
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 5
21 20 19 18
TIM17
Res. Res. Res.
EN
rw
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
TIM16
Res.
EN
rw
1 0
Res. Res.