Figure 165. Generation Of 2 Phase-Shifted Pwm Signals With 50% Duty Cycle - STMicroelectronics STM32WL5 Series Reference Manual

Advanced-control timer (TIM1)

Figure 165. Generation of 2 phase-shifted PWM signals with 50% duty cycle

0
Counter register
OC1REFC
CCR1=0
CCR2=8
OC3REFC
CCR3=3
CCR4=5
25.3.13 Combined PWM mode
Combined PWM mode allows two edge or center-aligned PWM signals to be generated with
programmable delay and phase shift between respective pulses. While the frequency is
determined by the value of the TIMx_ARR register, the duty cycle and delay are determined
by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or
AND logical combination of two reference PWMs:
–
–
Combined PWM mode can be selected independently on two channels (one OCx output per
pair of CCR registers) by writing '1100' (Combined PWM mode 1) or '1101' (Combined PWM
mode 2) in the OCxM bits in the TIMx_CCMRx register.
When a given channel is used as combined PWM channel, its complementary channel must
be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and
the other in Combined PWM mode 2).
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
Figure 166
mode, obtained with the following configuration:
–
–
–
–
754/1450
1 2 3 4
OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2
OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4
represents an example of signals that can be generated using Asymmetric PWM
Channel 1 is configured in Combined PWM mode 2,
Channel 2 is configured in PWM mode 1,
Channel 3 is configured in Combined PWM mode 2,
Channel 4 is configured in PWM mode 1.
5 6 7 8 7
RM0453 Rev 5
6 5 4 3 2
RM0453
1 1 0 1
MS33117V1