STMicroelectronics STM32WL5 Series Reference Manual page 439

RM0453
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 ECCL: ECC lock
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the flash ECC error connection to TIM1/16/17 break input.
0: ECC error disconnected from TIM1/16/17 break input.
1: ECC error connected to TIM1/16/17 break input.
Bit 2 PVDL: PVD lock enable bit
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PLS[2:0] in the
PWR_CR2R register.
0: PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PLS[2:0] bits can be
programmed by the application.
1: PVD interrupt connected to TIM1/16/17 break input. PVDE and PLS[2:0] bits are read only.
Bit 1 SPL: SRAM2 parity lock bit
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs.
0: SRAM2 parity error signal disconnected from TIM1/16/17 break inputs
1: SRAM2 parity error signal connected to TIM1/16/17 break inputs
Bit 0 CLL: CPU1 LOCKUP (Hardfault) output enable bit
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the connection of CPU1 LOCKUP (Hardfault) output to TIM1/16/17 break inputs.
0: CPU1 LOCKUP output disconnected from TIM1/16/17 break inputs
1: CPU1 LOCKUP output connected to TIM1/16/17 break inputs
11.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)
Address offset: 0x020
Reset value: 0x0000 0000
31 30 29
P31WP P30WP P29WP P28WP P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP
rs rs rs
15 14 13
P15WP P14WP P13WP P12WP P11WP P10WP P9WP
rs rs rs
Bits 31:0 PxWP: SRAM2 1 Kbyte page x write protection (x = 31 to 0)
These bits are set by software and cleared only by a system reset.
0: Write protection of SRAM2 1 Kbyte page x is disabled.
1: Write protection of SRAM2 1 Kbyte page x is enabled.
28 27 26 25
rs rs rs rs
12 11 10 9
rs rs rs rs
System configuration controller (SYSCFG)
24 23 22
rs rs rs
8 7 6
P8WP P7WP P6WP P5WP
rs rs rs
RM0453 Rev 5
21 20 19 18
rs rs rs rs
5 4 3 2
P4WP P3WP P2WP
rs rs rs rs
17 16
rs rs
1 0
P1WP P0WP
rs rs
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