Figure 143. Counter Timing Diagram, Internal Clock Divided By 2; Figure 144. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36 - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag

Figure 144. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

Figure 143. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
0003
(UIF)
CK_PSC
CNT_EN
0034
(UIF)
RM0453 Rev 5
Advanced-control timer (TIM1)
0002 0001 0000
0035
0001 0002 0003
MS31190V1
0036 0035
MS31191V1
735/1450
821