Figure 280. Data Reception - STMicroelectronics STM32WL5 Series Reference Manual

Inter-integrated circuit (I2C) interface
communication control bits, as well as status bits come back to their reset value. The
configuration registers are not impacted.
Here is the list of impacted register bits:
1. I2C_CR2 register: START, STOP, NACK
2. I2C_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF, BERR,
ARLO, OVR
and in addition when the SMBus feature is supported:
1. I2C_CR2 register: PECBYTE
2. I2C_ISR register: PECERR, TIMEOUT, ALERT
PE must be kept low during at least three APB clock cycles in order to perform the software
reset. This is ensured by writing the following software sequence:
1. Write PE = 0
2. Check PE = 0
3. Write PE = 1
34.4.7 Data transfer
The data transfer is managed through transmit and receive data registers and a shift
register.
Reception
The SDA input fills the shift register. After the eighth SCL pulse (when the complete data
byte is received), the shift register is copied into I2C_RXDR register if it is empty
(RXNE = 0). If RXNE = 1, meaning that the previous received data byte has not yet been
read, the SCL line is stretched low until I2C_RXDR is read. The stretch is inserted between
the eighth and ninth SCL pulse (before the acknowledge pulse).
SCL
Shift register
RXNE
I2C_RXDR
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Figure 280. Data reception

xx data1
data0
RM0453 Rev 5
ACK pulse ACK pulse
xx data2
rd data0 rd data1
data1
RM0453
legend:
SCL
stretch
xx
data2
MS19848V1