RM0453
36.3
LPUART implementation
The table(s) below describe(s) LPUART implementation. It(they) also include(s) USARTs for
comparison.
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode (Master/Slave)
Smartcard mode
Single-wire Half-duplex communication
IrDA SIR ENDEC block
LIN mode
Dual clock domain and wake-up from low-power mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
USART data length
Tx/Rx FIFO
Tx/Rx FIFO size
Wake-up from Stop mode
1. X = supported.
2. Wake-up supported from Stop 0 and Stop 1 modes.
3. Wake-up supported from Stop 0, Stop 1 and Stop 2 modes.
Low-power universal asynchronous receiver transmitter (LPUART)
Table 247. USART / LPUART features
USART /LPUART modes/features
(1)
RM0453 Rev 5
USART1/2
LPUART1
X
X
X
X
X
X
X
X
X
X
X
X
X
7, 8 and 9 bits
X
8
(2)
X
X
X
X
X
-
-
X
-
-
X
-
-
-
X
X
(3)
1203/1450
1253
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