STMicroelectronics STM32WL5 Series Reference Manual page 216

Sub-GHz radio (SUBGHZ)
5.10.30 Sub-GHz radio synchro timeout register
(SUBGHZ_LSYNCTIMEOUTR)
Address offset: 0x706
Reset value: 0x00
7 6
r r
Bits 7:0 SYNCTIMEOUT[7:0]: TimeoutValue = synchtimeout[7:3]*2^(2*synchtimeout[2:0]+1)
5.10.31 Sub-GHz radio LoRa IQ polarity MSB register (SUBGHZ_LIQPOLR)
Address offset: 0x735
Reset value: 0x00
7 6
Res Res
Bits 7:0 Reserved, must be kept at reset value.
5.10.32 Sub-GHz radio LoRa IQ polarity LSB register (SUBGHZ_LIQPOLR)
Address offset: 0x736
Reset value: 0x00
7 6
Res Res
Bits 7:0 Reserved, must be kept at reset value.
5.10.33 Sub-GHz radio LoRa synchronization word MSB register
(SUBGHZ_LSYNCRH)
Address offset: 0x740
Reset value: 0x14
7 6
rw rw
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5
r
If a detection has not occurred by TimeoutValue, it goes back to Standby mode, or restart
synch in continuous receive mode
Bits 7:3 synchtimeout(7:3) mantissa part
Bits 2:0 synchtimeout(2:0) exponent part
5
Res
5
Res
5
rw
4 3
SYNCTIMEOUT[7:0]
r r
4 3
Res Res
4 3
Res Res
4 3
SYNCWORD[15:8]
rw rw
RM0453 Rev 5
2 1
r r
2 1
Res Res
2 1
Res Res
2 1
rw rw
RM0453
0
r
0
Res
0
Res
0
rw