STMicroelectronics STM32WL5 Series Reference Manual page 809

RM0453
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as one of the break inputs is active
(BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting
only on the channels which are configured in output.
0: In response to a break 2 event. OC and OCN outputs are disabled
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
See OC/OCN enable description for more details
enable register
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if none of the break
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
This bit enables the complete break protection (including all sources connected to bk_acth
and BKIN sources, as per
0: Break function disabled
1: Break function enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details
enable register
0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled
or forced to idle state depending on the OSSI bit.
TIMx_CCER register).
(TIM1_CCER)).
inputs BRK and BRK2 is active)
in TIMx_BDTR register).
in TIMx_BDTR register).
TIMx_BDTR register).
(TIM1_CCER)).
is taken over by the GPIO logic, which forces a Hi-Z state).
or CCxNE=1 (the output is still controlled by the timer).
bits in TIMx_BDTR register).
(Section 25.4.11: TIM1 capture/compare
Figure 171: Break and Break2 circuitry
(Section 25.4.11: TIM1 capture/compare
RM0453 Rev 5
Advanced-control timer (TIM1)
overview).
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