STMicroelectronics STM32WL5 Series Reference Manual page 41

RM0453
38.6.16 DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . . . 1347
38.6.17 DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . . 1347
38.6.18 DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . . . 1347
38.6.19 DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . . 1348
38.6.20 DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . . 1348
38.6.21 DWT register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
38.7 Cross trigger interface (CTI) and cross trigger matrix (CTM) . . . . . . . . 1351
38.7.1
38.8 CPU1 ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
38.8.1
38.8.2
38.8.3
38.8.4
38.8.5
38.8.6
38.8.7
38.8.8
38.8.9
38.8.10 CPU1 ROM CoreSight component identity register 3 (ROM_CIDR3) 1378
38.8.11 CPU1 ROM table register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
38.9 CPU1 breakpoint unit (FPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379
38.9.1
38.9.2
38.9.3
38.9.4
38.9.5
38.9.6
38.9.7
38.9.8
38.9.9
38.9.10 FPB CoreSight peripheral identity register 1 (FPB_CIDR1) . . . . . . . 1384
38.9.11 FPB CoreSight component identity register 2 (FPB_CIDR2) . . . . . . 1385
38.9.12 FPB CoreSight component identity register 3 (FPB_CIDR3) . . . . . . 1385
38.9.13 CPU1 FPB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
38.10 CPU1 instrumentation trace macrocell (ITM) . . . . . . . . . . . . . . . . . . . . 1387
38.10.1 ITM stimulus register x (ITM_STIMRx) . . . . . . . . . . . . . . . . . . . . . . . 1387
38.10.2 ITM trace enable register (ITM_TER) . . . . . . . . . . . . . . . . . . . . . . . . 1388
CTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
CPU1 ROM memory type register (ROM_MEMTYPER) . . . . . . . . . . 1373
CPU1 ROM CoreSight peripheral identity register 4 (ROM_PIDR4) . 1374
CPU1 ROM CoreSight peripheral identity register 0 (ROM_PIDR0) . 1374
CPU1 ROM CoreSight peripheral identity register 1 (ROM_PIDR1) . 1375
CPU1 ROM CoreSight peripheral identity register 2 (ROM_PIDR2) . 1375
CPU1 ROM CoreSight peripheral identity register 3 (ROM_PIDR3) . 1376
CPU1 ROM CoreSight component identity register 0 (ROM_CIDR0) 1376
CPU1 ROM CoreSight peripheral identity register 1 (ROM_CIDR1) . 1377
CPU1 ROM CoreSight component identity register 2 (ROM_CIDR2) 1377
FPB control register (FPB_CTRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1379
FPB remap register (FPB_REMAPR) . . . . . . . . . . . . . . . . . . . . . . . . 1380
FPB comparator register x (FPB_COMPxR) . . . . . . . . . . . . . . . . . . . 1380
FPB CoreSight peripheral identity register 4 (FPB_PIDR4) . . . . . . . 1381
FPB CoreSight peripheral identity register 0 (FPB_PIDR0) . . . . . . . 1382
FPB CoreSight peripheral identity register 1 (FPB_PIDR1) . . . . . . . 1382
FPB CoreSight peripheral identity register 2 (FPB_PIDR2) . . . . . . . 1383
FPB CoreSight peripheral identity register 3 (FPB_PIDR3) . . . . . . . 1383
FPB CoreSight component identity register 0 (FPB_CIDR0) . . . . . . 1384
RM0453 Rev 5
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