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Reset and clock control (RCC)
Bit 12 SPI1RST: SPI1 reset
Bit 11 TIM1RST: Timer 1 reset
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCRST: ADC reset
Bits 8:0 Reserved, must be kept at reset value.
7.4.14
RCC APB3 peripheral reset register (RCC_APB3RSTR)
Address offset: 0x044
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SUBGHZSPIRST: Sub-GHz radio SPI reset
326/1450
This bit is set and cleared by software.
0: No effect
1: SPI1 reset
This bit is set and cleared by software.
0: No effect
1: TIM1 reset
This bit is set and cleared by software.
0: No effect
1: ADC reset
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit is set and cleared by software.
0: No effect
1: Sub-GHz radio SPI reset
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0453
17
16
Res.
Res.
1
0
Res.
rw
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