STMicroelectronics STM32WL5 Series Reference Manual page 346

Reset and clock control (RCC)
Bit 2 LSEBYP: LSE oscillator bypass
This bit is set and cleared by software to bypass the LSE oscillator. It can be written only
when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: LSE oscillator ready
This bit is set and cleared by hardware to indicate when the external 32 kHz oscillator is
stable.
0: LSE oscillator not ready
1: LSE oscillator ready
Note: Once the LSEON bit is cleared, this bit goes low after six LSE clock cycles.
Bit 0 LSEON: LSE oscillator enable
This bit is set and cleared by software.
0: LSE oscillator off
1: LSE oscillator on
Note: The LSE clock is directly forwarded to the RTC. To enable the LSE clock to other
7.4.31 RCC control/status register (RCC_CSR)
Address offset: 0x094
Reset value: 0x0C01 C600
(Reset by NRST pad, except reset flags by POR only, not reset by wake-up from Standby)
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31 30 29
LPWR WWDG IWDG
RSTF RSTF RSTF RSTF
r r r
15 14 13
RF
RFRST Res.
RSTF
rw r
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system peripherals (USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO,
MSI PLL mode), LSE must be enabled with the LSESYSEN bit.
28 27 26 25
SFT BOR PIN OBLRS
RSTF RSTF TF
r r r r
12 11 10 9
Res. MSISRANGE[3:0]
rw rw rw
24 23 22
RFILA
RMVF Res.
RSTF
r rw
8 7 6
Res. Res.
rw
RM0453 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
LSI
Res. Res. Res.
PRE
rw
RM0453
17 16
Res. Res.
1 0
LSI
LSION
RDY
r rw