STMicroelectronics STM32WL5 Series Reference Manual page 510

Extended interrupts and event controller (EXTI)
EXTI
Acronym
o
n
45 Radio Busy
46 CDBGPWRUPREQ
1. For correct operation, the EXTI direct event EXTI_C2IMRm.IMb bit must be set to 0 before CPU1 uses this di-
rect event.
2. For correct operation, the EXTI direct event EXTI_C1IMRm.IMb bit must be set to 0 before CPU2 uses this di-
rect event.
3. For correct operation, the EXTI configurable event EXTI_C2IMRm.IMb and EXTI_C2EMRm.EMb bits must
both be set to 0 before CPU1 uses this configurable event.
4. For correct operation, the EXTI configurable event EXTI_C1IMRm.IMb and EXTI_C1EMRm.EMb bits must
both be set to 0 before CPU2 uses this configurable event.
16.4 EXTI functional description
Depending on the EXTI event input type and wake-up targets, different logic
implementations are used. The applicable features are controlled from register bits as
detailed below:
•
Active trigger edge enable
–
–
•
Software trigger
EXTI software interrupt event register (EXTI_SWIER1)
EXTI software interrupt event register (EXTI_SWIER2)
•
Interrupt pending flag
EXTI pending register (EXTI_PR1)
EXTI pending register (EXTI_PR2)
•
CPU wake-up and interrupt enable
EXTI interrupt mask register (EXTI_CnIMR1)
EXTI interrupt mask register (EXTI_CnIMR2)
•
CPU wake-up and event enable
EXTI event mask register (EXTI_CnEMR1)
EXTI event mask register (EXTI_CnEMR2)
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Table 93. Wake-up interrupts (continued)
Description
RFBUSY wake-up
Debug power-up request wake-up
by rising edge selection
EXTI rising trigger selection register (EXTI_RTSR1)
EXTI rising trigger selection register (EXTI_RTSR2)
by falling edge selection
EXTI falling trigger selection register (EXTI_FTSR1)
EXTI falling trigger selection register (EXTI_FTSR2)
Configurable
RM0453 Rev 5
EXTI type Event
No CPU1 and CPU2
Direct No CPU1 and CPU2
RM0453
Wake-up