STMicroelectronics STM32WL5 Series Reference Manual page 925

RM0453
27.4.4 TIMx status register (TIMx_SR)(x = 16 to 17)
Address offset: 0x10
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF: Break interrupt flag
Bit 6 Reserved, must be kept at reset value.
Bit 5 COMIF: COM interrupt flag
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
12 11 10 9
Res. Res. CC1OF
rc_w0
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to '0'.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred
1: An active level has been detected on the break input
This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE,
CCxNE, OCxM– have been updated). It is cleared by software.
0: No COM event occurred
1: COM interrupt pending
This flag is set by hardware. It is cleared by software (input capture or output compare
mode) or by reading the TIMx_CCR1 register (input capture mode only).
0: No compare match / No input capture occurred
1: A compare match or an input capture occurred
If channel CC1 is configured as output: this flag is set when the content of the counter
TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of
TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the
counter overflow (in up-counting and up/down-counting modes) or underflow (in down-
counting mode). There are 3 possible options for flag setting in center-aligned mode, refer
to the CMS bits in the TIMx_CR1 register for the full description.
If channel CC1 is configured as input: this bit is set when counter value has been
captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge
sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
General-purpose timers (TIM16/TIM17)
8 7 6
Res. BIF Res. COMIF
rc_w0 rc_w0
RM0453 Rev 5
5 4 3 2
Res. Res. Res.
1 0
CC1IF UIF
rc_w0 rc_w0
925/1450
944