Table 77. Dma1 And Dma2 Implementation - STMicroelectronics STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
13.3
DMA implementation
13.3.1
DMA1 and DMA2
DMA1 and DMA2 are implemented with the hardware configuration parameters shown
in
Table
77.
Number of channels
Security
13.3.2
DMA request mapping
The DMA controller is connected to DMA requests from the AHB/APB peripherals through
the DMAMUX peripheral.
For the mapping of the different requests, refer to the
implementation.

Table 77. DMA1 and DMA2 implementation

Feature
RM0453 Rev 5
Direct memory access controller (DMA)
DMA1
7
1 (supported)
Section 14.3: DMAMUX
DMA2
7
1 (supported)
455/1450
479

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