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Inter-processor communication controller (IPCC)
9.4.5
IPCC processor 2 control register (IPCC_C2CR)
Address offset: 0x010
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 TXFIE: Processor 2 transmit channel free interrupt enable
Associated with IPCC_C2TOC1SR.
1: Enable an unmasked processor 2 transmit channel free to generate a TX free interrupt.
0: Processor 2 TX free interrupt disabled
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 RXOIE: Processor 2 receive channel occupied interrupt enable
Associated with IPCC_C1TOC2SR.
1: Enable an unmasked processor 2 receive channel occupied to generate an RX occupied
interrupt.
0: Processor 2 RX occupied interrupt disabled
9.4.6
IPCC processor 2 mask register (IPCC_C2MR)
Address offset: 0x014
Reset value: 0xFFFF FFFF
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:16 CHnFM: Processor 2 transmit channel n free interrupt mask (n = 6 to 1).
Associated with IPCC_C2TOC1SR.CHnF
1: Transmit channel n free interrupt masked.
0: Transmit channel n free interrupt not masked.
Bits 15:6 Reserved, must be kept at reset value.
396/1450
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
21
CH6
Res.
Res.
Res.
FM
rw
8
7
6
CH6
Res.
Res.
Res.
OM
rw
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
20
19
18
CH5
CH4
CH3
FM
FM
FM
rw
rw
rw
5
4
3
2
CH5
CH4
CH3
OM
OM
OM
rw
rw
rw
RM0453
17
16
Res.
TXFIE
rw
1
0
Res.
RXOIE
rw
17
16
CH2
CH1
FM
FM
rw
rw
1
0
CH2
CH1
OM
OM
rw
rw
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