STMicroelectronics STM32WL5 Series Reference Manual page 70

Memory and bus architecture
Table 3. Memory security and privilege access (continued)
SoC level memory area
Secure privileged
Secure unprivileged
Non-secure privileged
Non-secure unprivileged
Secure privileged
Secure unprivileged
Non-secure privileged
Non-secure unprivileged
1. Access to the hide protection secure privileged area is disabled by flash memory hide protection secure privileged
HDPADIS bit.
2. Read access returns a zero value, write access is ignored and, in both cases, an illegal access event is generated.
3. The secure privileged and unprivileged, read and execute protected pages cannot be written by a secure unprivileged
access. However it can be erased by a secure unprivileged page erase.
4. Privileged area start address < secure area start address.
5. Execution from SRAM1 and SRAM2 can be disabled by the execute never feature available from the MPU in the respective
CPU.
6. Read access returns a zero value, write access is ignored and, in both cases, an illegal access event is generated. When
RDP level is 1 and CPU1 boots from SRAM1, SRAM2 is locked and no illegal access event is generated.
70/1450
no
access
(5) (5)
ex , ex ,
(2)
rd, wr rd, wr
(5)
ex ,
rd, wr
no
access
(2)(4)
rd, wr rd, wr
rd, wr
no
access
(5) (5)
ex , ex ,
(2)
rd, wr rd, wr
(5)
ex ,
rd, wr
no
access
(2)(4)
rd, wr rd, wr
rd, wr
RM0453 Rev 5
no
access
no
(6)
access
rd, wr
(6)
(5)
ex ,
rd, wr
(5)
ex ,
rd, wr
no
access
no
(6)
access
(6)
rd, wr
(5)
ex ,
rd, wr
(5)
ex ,
rd, wr
RM0453
no
access
no
(2)(6)
access
no
(2)(6)
access
rd, wr
(2)(6)
no
access
(2)(4)
rd, wr
rd, wr rd, wr
no
access
no
(2)
access
no
(2)
access
rd, wr
(2)
no
access
(2)(4)
rd, wr
rd, wr rd, wr