Figure 285. Transfer Bus Diagrams For I2C Slave Transmitter (Mandatory Events Only) - STMicroelectronics STM32WL5 Series Reference Manual

Inter-integrated circuit (I2C) interface

Figure 285. Transfer bus diagrams for I2C slave transmitter (mandatory events only)

Example I2C slave transmitter 3 bytes with 1st data flushed,
NOSTRETCH=0:
S Address
TXE
EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF
EV2: TXIS ISR: wr data1
EV3: TXIS ISR: wr data2
EV4: TXIS ISR: wr data3
EV5: TXIS ISR: wr data4 (not sent)
Example I2C slave transmitter 3 bytes without 1st data flush,
NOSTRETCH=0:
S Address
TXE
EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF
EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)
Example I2C slave transmitter 3 bytes, NOSTRETCH=1:
S
EV1
TXE
EV1: wr data1
EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)
EV5: STOPF ISR: (optional: set TXE and TXIS), set STOPCF
1066/1450
ADDR TXIS
TXIS
A
data1 A
EV2
EV3
EV1
TXIS
ADDR TXIS
A data1 A
EV2
EV1
TXIS TXIS
Address data1 A
A
EV2 EV3
TXIS TXIS
data3
A
data2
EV4 EV5
TXIS
data2 A data3
EV3 EV4
TXIS
data2 A data3 NA P
EV4
RM0453 Rev 5
legend:
SCL stretch
NA P
legend :
transmission
reception
SCL stretch
NA P
legend:
transmission
STOPF
reception
SCL stretch
EV5
RM0453
transmission
reception
MS19853V2