Sub-Ghz Radio Regulator Drive Control Register; (Subghz_Regdrvcr); Sub-Ghz Radio Smps Control 2 Register (Subghz_Smpsc2R) - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
5.10.59

Sub-GHz radio regulator drive control register

(SUBGHZ_REGDRVCR)

Address offset: 0x91F
Reset value: 0x08
This register is retained in Sleep mode but lost in Deep-Sleep mode.
7 6
Res Res
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:1 TRIM[2:0]: Regulator drive trimming
Bit 0 EN: Regulator drive enable
5.10.60

Sub-GHz radio SMPS control 2 register (SUBGHZ_SMPSC2R)

Address offset: 0x923
Reset value: 0x06
This register is retained in Sleep mode but lost in Deep-Sleep mode.
7 6
Res Res
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:1 DRV[1:0]: SMPS maximum drive capability.
Bit 0 Reserved, must be kept at reset value.
5
Res
000: 1.22
001: 1.24
010: 1.26
011: 1.28
100: 1.30(default)
101: 1.32
110: 1.34
5
Res
0x0: 20 mA
0x1: 40 mA
0x2: 60 mA
0x3: 100 mA (default)
4 3
Res
rw
4 3
Res Res
RM0453 Rev 5
Sub-GHz radio (SUBGHZ)
2 1
TRIM[2:0
rw rw
2 1
DRV[1:0]
rw rw
0
EN
rw
0
Res
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