Table 199. Prescaler Division Ratios; Figure 263. Glitch Filter Timing Diagram - STMicroelectronics STM32WL5 Series Reference Manual

Low-power timer (LPTIM)
CLKMUX
Input
Filter out
Note: In case no internal clock signal is provided, the digital filter must be deactivated by setting
the CKFLT and TRGFLT bits to '0'. In that case, an external analog filter may be used to
protect the LPTIM external inputs against glitches.
28.4.6 Prescaler
The LPTIM 16-bit counter is preceded by a configurable power-of-2 prescaler. The prescaler
division ratio is controlled by the PRESC[2:0] 3-bit field. The table below lists all the possible
division ratios:
28.4.7 Trigger multiplexer
The LPTIM counter may be started either by software or after the detection of an active
edge on one of the 8 trigger inputs.
TRIGEN[1:0] is used to determine the LPTIM trigger source:
•
When TRIGEN[1:0] equals '00', The LPTIM counter is started as soon as one of the
CNTSTRT or the SNGSTRT bits is set by software. The three remaining possible
values for the TRIGEN[1:0] are used to configure the active edge used by the trigger
inputs. The LPTIM counter starts as soon as an active edge is detected.
•
When TRIGEN[1:0] is different than '00', TRIGSEL[2:0] is used to select which of the 8
trigger inputs is used to start the counter.
950/1450

Figure 263. Glitch filter timing diagram

2 consecutive samples

Table 199. Prescaler division ratios

programming
000
001
010
011
100
101
110
111
RM0453 Rev 5
2 consecutive samples
dividing factor
RM0453
Filtered
MS32490V1
/1
/2
/4
/8
/16
/32
/64
/128