Flash Wrp Area B Address Register (Flash_Wrp1Br) - STMicroelectronics STM32WL5 Series Reference Manual

Embedded flash memory (FLASH)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 WRP1A_END[6:0]: WRP area A end offset
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1A_STRT[6:0]: WRP area A start offset
4.10.12

FLASH WRP area B address register (FLASH_WRP1BR)

Address offset: 0x030
Reset value: 0xFF80 FFFF
Default reset value from ST production is given as 0b1111 1111 1XXX XXXX 1111 1111
1XXX XXXX, the option bits are loaded with user values from flash memory at reset release.
Access: no wait state when no flash memory operation is ongoing. Word, half-word and byte
access.
This register can only be written by the CPU1 in RDP level 0 or RDP level 1.
When the system is secure (ESE = 1), this register is further more protected by the
PRIVMODE. When privilege protection is enabled in PRIVMODE, this register provides
write access privilege and can only be written by a privileged access. Unprivileged write
access is ignored and an illegal access event is generated. Unprivileged read access is still
allowed.
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 WRP1B_END[6:0]: WRP area B end offset
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1B_STRT[6:0]: WRP area B start offset
142/1450
Contains the last 2-Kbyte page of the WRP area A.
Contains the first 2-Kbyte page of the WRP area A.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
WRPB1_END contains the last 2-Kbyte page of the WRP area B.
WRPB1_END contains the first 2-Kbyte page of the WRP area B.
24 23 22
Res. Res.
rw
8 7 6
Res. Res.
rw
RM0453 Rev 5
21 20 19 18
WRP1B_END[6:0]
rw rw rw rw
5 4 3 2
WRP1B_STRT[6:0]
rw rw rw rw
RM0453
17 16
rw rw
1 0
rw rw