Figure 7. Sequential 16 Bits Instructions Execution - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
The figure below shows the execution of sequential 16-bit instructions with and without
prefetch when three wait states are needed to access the flash memory.
@
1
Read ins 1, 2, 3, 4
@
1
Read ins 1, 2, 3, 4

Figure 7. Sequential 16 bits instructions execution

F D
WAIT
1 1
@ F
2 2
@
3
ins 1 ins 2
fetch fetch
Gives ins 1, 2, 3, 4
F D
WAIT
1 1
@ F
2 2
@
3
ins 1 ins 2
fetch fetch
Gives ins 1, 2, 3, 4
Read ins 5, 6, 7, 8
RM0453 Rev 5
Embedded flash memory (FLASH)
E
1
D E
2 2
F D E
3 3 3
@ F D E
4 4 4 4
@
WAIT
5
@
6
ins 3 ins 4
fetch fetch
Read ins 5, 6, 7, 8
E
1
D E
2 2
F D E
3 3 3
@ F D E
4 4 4 4
@ F D E
5 5 5 5
@ F D
6 6 6
@ F
7 7
@
8
ins 3 ins 4 ins 5 ins 6
fetch fetch fetch fetch
Gives ins 5, 6, 7, 8
Read ins 9, 10, ...
WITHOUT PREFETCH
F D E
5 5 5
F D E
6 6 6
@ F D
7 7 7
@ F
8 8
ins 5 ins 6 ins 7 ins 8
fetch fetch fetch fetch
Gives ins 5, 6, 7, 8
WITH PREFETCH
E
6
D
7
Cortex-M4 pipeline
F
8
@ F
6 6
ins 7 ins 8
AHB protocol
fetch fetch
@: address requested
F: Fetch stage
D: Decode stage
E: Execute stage
D E
6 6
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