Figure 289. Master Clock Generation - STMicroelectronics STM32WL5 Series Reference Manual

Inter-integrated circuit (I2C) interface RM0453

Figure 289. Master clock generation

SCL master clock generation
SCL high level detected
SCLH counter starts
t
SCLH
SYNC2
SCLL
t
SYNC1
SCL
SCL low level detected
SCL released
SCLL counter starts
SCL driven low
SCL master clock synchronization
SCL high level detected
SCL high level detected SCL high level detected
SCLH counter starts
SCLH counter starts SCLH counter starts
SCLH
SCLH
SCLH
SCLL SCLL
SCL driven low by
SCL driven low by
another device
another device
SCL low level detected
SCLL counter starts
SCL low level detected
SCLL counter starts SCL released
MS19858V1
1070/1450 RM0453 Rev 5