Watchdog Clock; True Rng Clock; Clock-Out Capability - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
7.2.17

Watchdog clock

If the independent watchdog (IWDG) is started by an hardware option or a software access,
the LSI clock is forced on.
If the LSI oscillator is disabled when starting the IWDG, the LSI oscillator is forced on. After
the LSI oscillator temporization, the clock is provided to the IWDG.
7.2.18

True RNG clock

The true random number generator (RNG) seed clock is derived from the MSI, from the PLL
output or from the LSE or LSI clock. It can reach 48 MHz and can be divided by a prescalers
values by configuring the true RNG register. It is asynchronous to the AHB clock.
7.2.19

Clock-out capability

•
MCO
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. One of the following clock signals can be selected as the MCO
clock:
–
–
–
–
–
–
–
–
–
The selection is controlled by the MCOSEL[3:0] bits in the
register
the
The clock on MCO is only available in Run modes and is not available in Stop, Standby
and Shutdown modes.
•
LSCO
Another output (LSCO) allows one of the following low-speed clocks to be output onto
the external LSCO pin:
–
–
The selection is controlled by the LSCOSEL bit and enabled with the LSCOEN bit in
the
The clock on LSCO is available in Run, Stop, and Standby and Shutdown modes.
The configuration registers of the corresponding GPIO port must be programmed in
alternate function mode.
SYSCLK
MSI
HSI16 (only available when enabled by HSION)
HSE32
PLLRCLK
LSI
LSE
PLLPCLK
PLLQCLK
(RCC_CFGR). The selected clock can be divided with the MCOPRE[2:0] bits in
RCC clock configuration register
LSI
LSE
RCC backup domain control register
(RCC_CFGR).
(RCC_BDCR).
RM0453 Rev 5
Reset and clock control (RCC)
RCC clock configuration
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