Figure 242. Counter Timing Diagram, Internal Clock Divided By 4; Figure 243. Counter Timing Diagram, Internal Clock Divided By N - STMicroelectronics STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
General-purpose timers (TIM16/TIM17)

Figure 242. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0035
0036
0000
0001
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31080V2

Figure 243. Counter timing diagram, internal clock divided by N

CK_PSC
Timerclock = CK_CNT
1F
Counter register
20
00
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31081V2
RM0453 Rev 5
899/1450
944

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