Figure 203. Counter Timing Diagram, Internal Clock Divided By 2; Figure 204. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36 - STMicroelectronics STM32WL5 Series Reference Manual

General-purpose timer (TIM2)
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag

Figure 204. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
834/1450

Figure 203. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
0003
(UIF)
CK_PSC
CNT_EN
0034
(UIF)
RM0453 Rev 5
0000
0002 0001
0035
RM0453
0002 0003
0001
MS31190V1
0036 0035
MS31191V1