Lse Clock; Figure 30. Lse Clock Sources - STMicroelectronics STM32WL5 Series Reference Manual

Reset and clock control (RCC)
The PLLQCLK and PLLRCLK output frequency must not exceed 48 MHz. The PLLPCLK
output frequency must not exceed 62 MHz.
The enable bits of the PLL output clock (PLLPEN, PLLQEN, PLLREN) can be modified at
any time without stopping the PLL. PLLREN cannot be cleared if PLLRCLK is used as
system clock.
7.2.5

LSE clock

The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It provides
a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for
clock/calendar or other timing functions.
The resonator and the load capacitors must be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. The loading
capacitance values must be adjusted according to the selected oscillator.
The LSE crystal is switched on and off using the LSEON bit in the
control register
runtime using the LSEDRV[1:0] bits in the
(RCC_BDCR)
on one side and low-power-consumption on the other side. The LSE drive can be decreased
to the lower drive capability (LSEDRV = 0) when the LSE is on. However, once LSEDRV is
selected, the drive capability can not be increased if LSEON = 1.
The LSERDY flag in the
whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not
released until this bit is set by hardware. An interrupt can be generated if enabled in the
RCC clock interrupt enable register
When enabled and ready the LSE clock can directly be used by the RTC. To be able to use
the clocks by other peripherals (LPTIMx, TIMx, USARTx, LPUARTx, system LSCO, MCO,
MSI PLL mode), the LSE system clock must be enabled with the LSESYSEN bit in the
backup domain control register
enabled, the LSE clock is used by the LSECSS and is available on the LSCO. A
LSESYSRDY flag is provided in the
indicate when LSE system clock is ready (due clock synchronization) after having been
enabled by the LSESYSEN.
296/1450

Figure 30. LSE clock sources

Clock source
Crystal/
ceramic
resonators
External
(RCC_BDCR). The crystal oscillator driving strength can be changed at
to obtain the best compromise between robustness and short start-up time
RCC backup domain control register (RCC_BDCR)
(RCC_CIER).
(RCC_BDCR). When the LSE clock is ready and LSECSS is
RM0453 Rev 5
Hardware configuration
OSC32_IN OSC32_OUT
C
L1
Load
capacitors
OSC32_IN
GPIO
External
clock source
RCC backup domain control register
RCC backup domain control register (RCC_BDCR)
C
L2
OSC32_OUT
RCC backup domain
indicates
RM0453
MSv62608V1
RCC
to