STMicroelectronics STM32WL5 Series Reference Manual page 56

List of figures
Figure 255. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
Figure 256. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 911
Figure 257. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 912
Figure 258. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
Figure 259. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
Figure 260. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
Figure 261. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
Figure 262. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
Figure 263. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Figure 264. LPTIM output waveform, single counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . . . . . . . 951
Figure 265. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Figure 266. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 952
Figure 267. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Figure 268. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Figure 269. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
Figure 270. IRTIM internal hardware connections with TIM16 and TIM17
Figure 271. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
Figure 272. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
Figure 273. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
Figure 274. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
Figure 275. TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
Figure 276. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
Figure 277. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Figure 278. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
Figure 279. I2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
Figure 280. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Figure 281. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Figure 282. Slave initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Figure 283. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . . . . . . . . . . . . 1064
Figure 284. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . . . . . . . . . . . . 1065
Figure 285. Transfer bus diagrams for I2C slave transmitter (mandatory events only) . . . . . . . . . . . 1066
Figure 286. Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . . . . . . . . . . . . . 1067
Figure 287. Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . . . . . . . . . . . . . 1068
Figure 288. Transfer bus diagrams for I2C slave receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
Figure 289. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
Figure 290. Master initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
Figure 291. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
Figure 292. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
Figure 293. Transfer sequence flow for I2C master transmitter for N ≤ 255 bytes . . . . . . . . . . . . . . 1074
Figure 294. Transfer sequence flow for I2C master transmitter for N > 255 bytes . . . . . . . . . . . . . . 1075
Figure 295. Transfer bus diagrams for I2C master transmitter
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
Figure 296. Transfer sequence flow for I2C master receiver for N ≤ 255 bytes . . . . . . . . . . . . . . . . 1078
Figure 297. Transfer sequence flow for I2C master receiver for N > 255 bytes . . . . . . . . . . . . . . . . 1079
Figure 298. Transfer bus diagrams for I2C master receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
Figure 299. Timeout intervals for t
Figure 300. Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . . . . 1087
56/1450
, t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
LOW:SEXT LOW:MEXT
RM0453 Rev 5
RM0453
. . . . . . . . . . . . . . . . . . . 973