Figure 276. I2C Block Diagram - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
34.4.1 I2C block diagram
The block diagram of the I2C interface is shown in
i2c_ker_ck
i2c_pclk
The I2C is clocked by an independent clock source, which allows the I2C to operate
independently from the PCLK frequency.
For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to

Figure 276. I2C block diagram

I2CCLK
Wake-up
on
address
match
PCLK
Section 34.3: I2C implementation.
Inter-integrated circuit (I2C) interface
Figure
Data control
Digital
Shift register
noise
filter
SMBUS
PEC
generation/
check
Clock control
Master clock
Digital
generation
noise
Slave clock
filter
stretching
SMBus
timeout
check
SMBus alert
control/status
Registers
APB bus
RM0453 Rev 5
276.
Analog
noise
GPIO
filter
logic
Analog
noise
GPIO
filter
logic
I2C_SDA
I2C_SCL
I2C_SMBA
MSv46198V2
1051/1450
1113